Wafer level hybrid bonding technology for wafer-to-wafer bonding is utilized in fabrication of three-dimensional integrated circuit (3D-IC) components, such as back-side illuminated (BSI) complementary metal-oxide semiconductor (CMOS) image sensors (CIS). When fabricating the BSI-CIS, a sensor wafer including BSI sensing integrated circuits arranged in array and a logic circuit wafer including logic circuit chips arranged in array are provided. The sensor wafer and the logic circuit wafer are bonded with each other through wafer level hybrid bonding technology such that the logic circuit wafer is stacked over the sensor wafer. Thereafter, the hybrid bonded sensor and logic circuit wafers are packaged and singulated to form BSI-CIS devices. During hybrid bonding process of the sensor wafer and the logic circuit wafer, copper extrusion and/or copper migration may generate at the bonding interface of the wafers. Accordingly, reliability of the hybrid bonded wafers deteriorates due to the above-mentioned copper extrusion and/or copper migration.